1. Field of the Invention
This invention relates generally to a cathode ray tube display terminal system which includes a cathode ray tube display subsystem, a central processor subsystem, and a plurality of peripheral subsystems, all coupled in common to a system bus. The invention relates particularly to apparatus which, in response to interrupt signals from one or more subsystems, generates address signals which call for firmware routines to process the interrupt from a selected subsystem.
2. Description of the Prior Art
A cathode ray display system is made up of a number of subsystems, including a central processor subsystem, all coupled to a common bus. When a subsystem requests attention, it sends an interrupt signal on the bus to the central processor subsystem. In the prior art system the central processor subsystem would poll the subsystems to determine which subsystem interrupted. The central processor subsystem would then process the interrupt and generate a unique interrupt vector address on the bus. This required the central processor to utilize hardware and firmware to poll all the devices in the subsystem, prioritize those devices with active interrupts and generate the unique interrupt vectored address to enter into the firmware interrupt service routine.
There are various other types of interrupt processing systems in the prior art which are coupled to provide interrupt service in response to an interrupt signal received from any one of a number of sources such as peripherals connected to an input/output bus. Typically the procedure followed for servicing interrupts from such peripherals first requires identifying the interrupting peripherals, next requesting the status of the peripheral and then updating the status. This procedure is relatively slow and in certain types of systems where interrupt routines are executed frequently, the acknowledge routine time may pose serious speed restraints on the total system. In one such interrupt system, as indicated in U.S. Pat. No. 3,881,174, the interrupt processing apparatus includes a computer which allows a peripheral, upon receiving an acknowledgement from a computer of an interrupt request which the peripheral previously generated to simultaneously provide the computer with its address and status thereby shortening the time required for the interrupt routine.
U.S. Pat. No. 4,030,075 describes a data processing system having a distributed priority network. This priority network is coupled with each of the units and indicates which is the highest priority unit requesting to transfer information over the bus. The priority network includes a priority bus with the units coupled closest to one end of the bus having a highest priority and units coupled at the other end of the bus having a lowest priority. All of the above systems have the disadvantage of having considerable hardware and time consuming cycles to perform the connection to the bus.
The Honeywell 7760 display system is a central processor subsystem which controls a fixed number of peripheral subsystems. The 7760 is described in "VIP 7760 Subsystem User's Reference Manual", AT45 Rev. 0, May 1978.
Each peripheral subsystem sends a unique request for interrupt signal to the central processor subsystem which makes the highest priority peripheral subsystem operative in the display system. The number of peripheral subsystems in the display system is limited to the throughput capability of the central processor subsystem. The interrupt and priority apparatus in the display system can readily process interrupts from the maximum number of peripheral subsystems.
However present day display systems having higher speed microprocessors in the central processor subsystem, with subsequent increased throughput capabilities, can process many more peripheral subsystems than can prior art display systems. The interrupt and priority apparatus of the prior art display systems, when required to process an increased number of peripheral subsystems, is costly and relatively slow so as to reduce the overall display system throughput.